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Data Sheet
Bit
ADE7854/ADE7858/ADE7868/ADE7878
Location
10
Bit Mnemonic
CF2DIS
Default Value
1
Description
When this bit is set to 1, the CF2 output is disabled. The respective digital to frequency
converter remains enabled even if CF2DIS = 1.
When this bit is set to 0, the CF2 output is enabled.
11
CF3DIS
1
When this bit is set to 1, the CF3 output is disabled. The respective digital to frequency
converter remains enabled even if CF3DIS = 1.
When this bit is set to 0, the CF3 output is enabled.
12
13
14
15
CF1LATCH
CF2LATCH
CF3LATCH
Reserved
0
0
0
0
When this bit is set to 1, the content of the corresponding energy registers is latched when a
CF1 pulse is generated. See the Synchronizing Energy Registers with CFx Outputs section.
When this bit is set to 1, the content of the corresponding energy registers is latched when a
CF2 pulse is generated. See the Synchronizing Energy Registers with CFx Outputs section.
When this bit is set to 1, the content of the corresponding energy registers is latched when a
CF3 pulse is generated. See the Synchronizing Energy Registers with CFx Outputs section.
Reserved. This bit does not manage any functionality.
Table 46. APHCAL, BPHCAL, CPHCAL Registers (Address 0xE614, Address 0xE615, Address 0xE616)
Bit
Location
9:0
Bit Mnemonic
PHCALVAL
Default Value
0000000000
Description
If the current leads the voltage, these bits can vary only between 0 and 383.
If the current lags the voltage, these bits can vary only between 512 and 575.
If the PHCALVAL bits are set with numbers between 384 and 511, the compensation behaves
like PHCALVAL set between 256 and 383.
If the PHCALVAL bits are set with numbers between 576 and 1023, the compensation
behaves like PHCALVAL bits set between 384 and 511.
15:10
Reserved
000000
Reserved. These bits do not manage any functionality.
Table 47. P HSIGN     Registe r (Address 0xE617)
Bit
Location
0
Bit Mnemonic
AWSIGN
Default Value
0
Description
0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase A is positive.
1: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase A is negative.
1
BWSIGN
0
0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase B is positive.
1: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase B is negative.
2
CWSIGN
0
0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase C is positive.
1: if the active power identified by Bit 6 (REVAPSEL) bit in the ACCMODE register (total of
fundamental) on Phase C is negative.
3
SUM1SIGN
0
0: if the sum of all phase powers in the CF1 datapath is positive.
1: if the sum of all phase powers in the CF1 datapath is negative. Phase powers in the CF1
datapath are identified by Bits[2:0] (TERMSEL1[x]) of the COMPMODE register and by
Bits[2:0] (CF1SEL[x]) of the CFMODE register.
4
AVARSIGN
0
0: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase A is positive. This bit is always 0 for ADE7854 .
1: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase A is negative.
5
BVARSIGN
0
0: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase B is positive. This bit is always 0 for ADE7854 .
1: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase B is negative.
6
CVARSIGN
0
0: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase C is positive. This bit is always 0 for ADE7854 .
1: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase C is negative.
Rev. H| Page 93 of 100
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